The present disclosure relates to solid state imaging devices in which pixels including photoelectric conversion elements are arranged in an array pattern.
Much attention has been paid to MOS-type solid state imaging devices due to their low power consumption, and high-speed imaging. The MOS-type solid state imaging devices have been and are being employed in various fields, such as cameras of mobile devices, on-board cameras, monitoring cameras, etc.
FIG. 7 shows a circuit diagram illustrating a structure of a conventional MOS-type solid state imaging device. As shown in FIG. 7, pixels 100 including photoelectric conversion elements (photodiodes) 101, respectively, are arranged in an array pattern to constitute an imaging region 200. Charges produced by photoelectric conversion of the photoelectric conversion element 101 are transferred to a floating diffusion layer 102 by a transfer transistor 103. The charges transferred to the floating diffusion layer 102 are amplified by an amplifier transistor 104, and are transferred to an output signal line 110 through a selection transistor 106 which is selected by a vertical shift register 108, and are output from an output end 111 through a horizontal shift register 109. A surplus of the charges accumulated in the floating diffusion layer 102 is discharged by a reset transistor 105 having a drain region connected to a power supply line 107.
FIG. 8 is a cross-sectional view illustrating a general structure of the pixels 100. As shown in FIG. 8, the photoelectric conversion elements 101, the floating diffusion layers 102, and source/drain regions of the amplifier transistors 104 are formed in a substrate 201. The pixels 100 adjacent to each other are electrically isolated from each other by an insulating isolation part 202.
Long wavelength light incident on the substrate 201, such as red light, travels to a deeper region in the substrate 201. Thus, when some of the charges produced by photoelectric conversion leak to the adjacent pixel 100, mixing of colors, or blooming may occur. To prevent the mixing of colors etc. due to the leakage of the charges, Japanese Patent Publication No. H11-284168, U.S. Pat. No. 5,859,462, etc. describe a method for forming a narrow and deep isolation diffusion layer 204 below a shallow isolation diffusion layer 203 formed below the insulating isolation part 202 as shown in FIG. 8.
When operating speed of the solid state imaging device is increased, and a potential of the substrate 210 in which the amplifier transistors 104 are formed varies during high-speed operation of the amplifier transistors, operation of the amplifier transistors becomes unstable. Thus, as shown in FIG. 8, high concentration well regions 205 are formed in the substrate 201 to form the amplifier transistors 104 in the high concentration well regions 205. This can reduce change in potential of the well regions 205 even when the amplifier transistors 104 are operated at high speed. Thus, the amplifier transistors 104 can stably be operated.